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PI6C105
Precision Clock Synthesizer for Mobile PCs
Features
* Two copies of CPU clock with VDD of 2.5V 5% * * * * * * * * * * 100 MHz or 66 MHz operation Six copies PCI clock (synchronous with CPU clock) 3.3V One copy of Ref. clock @ 14.31818 MHz (3.3VTTL) 48 MHz USB Clock, 24 MHz Super I/O clock I2C Serial Configuration Interface Spread Spectrum Modulation for CPUCLK, and PCICLK Low-cost 14.31818 MHz crystal oscillator input Power management control Isolated core VDD, VSS pins for noise reduction 28-pin SSOP and SOIC package (H)
Description
The PI6C105 is a high-speed, low-noise clock generator designed to work with the PI6C18x family of clock buffers to meet all clock needs for Mobile Intel Architecture platforms. CPU and chipset clock frequencies of 66.6 MHz and 100 MHz are supported. Split supplies of 3.3V and 2.5V are used. The 3.3V power supply powers a portion of the I/O and the core. The 2.5V is used to power the remaining outputs. 2.5V signaling follows JEDEC standard 8-X. Power sequencing of the 3.3V and 2.5V supplies is not required. An asynchronous PWR_DWN# signal may be used to power down (or up) the system in an orderly manner.
Block Diagram
Pin Configuration
XTAL_IN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 VSSREF VDDREF REF VDDCPU CPUCLK0 CPUCLK1 VSSCPU VDDCORE VSSCORE PCI_STOP# CPU_STOP# PWR_DWN# SDATA SCLK
XTAL_IN XTAL_OUT Spread# SEL100/66#
REF OSC 2 PLL1 CPU_STOP# DIV I2C 5
REF CPUCLK [0:1]
XTAL_OUT VSSPCI PCICLK_F PCICLK1 PCICLK2
SDATA SCLK
PCICLK [1:5] PCICLK_F
PCICLK3 PCICLK4 VDDPCI PCICLK5 VDDP2 48M/SPREAD# VSSP2 24M/SEL100/66#
28-Pin H
23 22 21 20 19 18 17 16 15
PCI_STOP#
PLL2
/2
48 MHz 24 MHz
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PI6C105 Precision Clock Synthesizer for Mobile PCs
Pin Description
Pin 1 2 3 4 5,6,7,8,10 9 11 Signal Name XTAL_IN XTAL_O UT VSSPCI PCICLK _F PCICLK [1:5] VDDPCI VDDP2 48 MHz/SPREAD# 12 48 MHz SPREAD# 13 VSSP2 24 MHz/SEL100/66# 14 24 MHz SEL100/66# 15 16 17 18 19 20 21 22 23,24 25 26 27 28 SCLK SDATA PWR_DWN# CPU_STO P# PCI_STO P# VSSCORE VDDCORE VSSCPU CPUCLK [0:1] VDDCPU REF VDDREF VSSREF 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 Qty. 1 1 1 1 5 1 1 14.318 MHz crystal input 14.318 MHz crystal input Ground for PCI clock outputs Free running PCI clock output PCI clock outputs, TTL compatible 3.3V Power for all PCI clock outputs (4,5,6,7,8,10) Power Supply for 24 MHz and 48 MHz outputs 48 MHz output or SPREAD# input. Internal pull up 48 MHz output for USB clock Active lowEnable Spread Spectrum mode, default disable. This is an input sampled during power up. Becomes 48 MHz output after power up Ground for 24 MHz and 48 MHz 24 MHz output or SEL100/66# input, internal pull up 24 MHz output for Super I/O Clock During power up this pin is SEL100/66# input, 24MHz output otherwise. Low = 66MHz, High = 100MHz Serial Clock for I2C interface. Internal Pull Up Serial Data for I2C interface. Internal Pull Up Active Lower Power Down, When active PLLs, crystal, and oscillator is off. CPUCLK s and PCICLK clocks are held low. Internal Pull Up Active Low. Stops all CPU clocks to low state. Internal Pull Up Active Low. Stops all PCICLK clocks to low state, except for PCICLK _F. Internal Pull Up Ground for chip core Power supply for chip core Ground for CPU clock outputs CPU and Host clock outputs 2.5V Power supply for CPU clock outputs 2.5V Buffered crystal output Power Supply for REF outputs Ground for REF outputs D e s cription
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PI6C105 Precision Clock Synthesizer for Mobile PCs
Select Functions
SEL100/66#
0 1
Function
66 MHz active 100 MHz active
Clock Enable Configuration
CPU_STOP# PCI_STOP# PWR_DWN# CPUCLK [0:1] PCICLK [1:5] PCICLK_F Othe r Clocks X 0 0 1 1 X 0 1 0 1 0 1 1 1 1 low low low 100/66 MHz 100/66 MHz low low 33 MHz low 33 MHz low 33 MHz 33 MHz 33 MHz 33 MHz stopped running running running running Crys tal off running running running running VCO's off running running running running
2-Wire I2C Control
The I2C interface permits individual enable/disable of each clock output and test mode enable. The PI6C105 is a slave receiver device. It can not be read back. Sub addressing is not supported. To change one of the control bytes, all preceding bytes must be sent. Every byte put on the SDATA line must be 8-bits long (MSB first), followed by an acknowledge bit generated by the receiving device. During normal data transfers, SDATA changes only when SCLK is LOW. Exceptions: A HIGH-to-LOW transition on SDATA while SCLK is HIGH indicates a start condition. A LOW-to-HIGH transition on SDATA, while SCLK is HIGH, is a stop condition and indicates the end of a data transfer cycle. Each data transfer is initiated with a start condition and ended with a stop condition. The first byte after a start condition is always a 7-bit address byte followed by a read/write bit. (HIGH = read from addressed device, LOW= write to addressed device). If the devices own address is detected, PI6C105 generates an acknowledge by pulling SDATA line LOW during ninth clock pulse, then accepts the following data bytes until another start or stop condition is detected. Following acknowledgment of the address byte (D2), two more bytes must be sent: 1. Command Code byte, and 2. Byte Count byte. Although the data bits on these two bytes are dont care, they must be sent and acknowledged.
PI6C105 I2C Address Assignment
A7
1
A6
1
A5
0
A4
1
A3
0
A2
0
A1
1
A0
0
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PI6C105 Precision Clock Synthesizer for Mobile PCs
Byte 3: Modes
Bit# 7 6 5 Pup 0 0 0 Pin# Name RSVD SS1 SS0 De s cription Reserved Spread Spectrum Select bit 1 Spread Spectrum Select bit 0 SS1 SS0 0 0 1 1 4 3 2 1 0 0 0 0 0 0 RSVD RSVD RSVD MODE1 MODE0 M1 0 0 1 1 M0 0 1 0 1 Normal Test Mode Reserved Hi- Z 0 1 0 1 66M 100M
- 0.6% - 0.6% Default - 1.2% - 1.0% - 1.8% - 1.5% - 2.4% - 2.0% Reserved Reserved Reserved Mode bit 1 Mode bit 0
Byte 4: Clock Controls (1 = Enabled, 0 = Disabled)
Bit # 7 6 5 4 3 2 1 0 1 23 Pup Pin # 12 14 Name 48MEN RSVD RSVD RSVD RSVD RSVD D e s cription 48 MHz Enable, Default is Enable Reserved Reserved Reserved Reserved Reserved
24MEN 24 MHz Enable, Default is Enable
CPU1EN CPUCLK 1 Enable, Default is Enable
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PI6C105 Precision Clock Synthesizer for Mobile PCs
Byte 5: PCI Clock Control (1 = Enabled, 0 = Disabled)
Bit # 7 6 5 4 3 2 1 0 1 10 8 7 6 5 Pup Pin # 4 Name Reserved PCI5EN PCI5 Enable, Default is Enable Reserved PCI4EN PCI4 Enable, Default is Enable PCI3EN PCI3 Enable, Default is Enable PCI2EN PCI2 Enable, Default is Enable PCI1EN PCI1 Enable, Default is Enable D e s cription PCIFEN PCI_F Enable, Default is Enable
Byte 6: REF Clock Control (1 = Enabled, 0 = Disabled)
Bit# 7 6 5 4 3 2 1 24 24 CPU0S1 CPU0S0 CPU0 Drive Select Bit 1 CPU0 Drive Select Bit 0 CPU0S1 CPU0S0 0 0 1 1 1 0 1 1 26 26 0 1 0 1 Disable Low Drive High Drive Medium Drive, Default RSVD Reserved Pup Pin# Name De s cription
REFS1REF Drive Select Bit 1 REFS0REF Drive Select Bit 0 REFS1 0 0 1 1 REFS0 0 1 0 1 Disable Low Drive High Drive Medium Drive, Default
Note: Outputs are disabled @ low state
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PI6C105 Precision Clock Synthesizer for Mobile PCs
SEL100/66# (pin 14) SS1 Byte 3 [6] SS0 Byte 3 [5] D own Spre ad 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 - 0.6% - 1.2% - 1.8% - 2.4% - 0.6% - 1.0% - 1.5% - 2.0%
D e s cription 66.6 MHz, - 0.6% down spread 66.6 MHz, - 1.2% down spread 66.6 MHz, - 1.8% down spread 66.6 MHz, - 2.4% down spread 100 MHz, - 0.6% down spread 100 MHz, - 1.0% down spread 100 MHz, - 1.5% down spread 100 MHz, - 2.0% down spread
Power Management Timing
Signal CPU_STOP# Signal State 0 (disabled) 1 (enabled) PCI_STOP# 0 (disabled) 1 (enabled) PWR_DWN# 1 (normal operation) 0 (power down) Late ncy No. of ris ing e dge s of fre e running PCICLK 1 1 1 1 3ms 2 max.
Notes: 1. Clock on/off latency is defined as the number of rising edges of free running PCICLKs between when the clock disable goes low/high to when the first valid clock comes out of the device. 2. Power-up latency is from when PWR_DWN# goes inactive (HIGH) to when the first valid clocks are driven from the device.
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PI6C105 Precision Clock Synthesizer for Mobile PCs
CPU_STOP#, which is an input signal used to turn off the CPU clocks for low power operation, is asserted asynchronously by the external clock control logic with the rising edge of the free running PCI clock and is internally synchronized to the external PCICLK_F output. All other clocks continue to run while the CPU clocks are
CPUCLK
(Internal)
disabled. The CPU clocks are always stopped in a low state and started guaranteeing that the high pulse width is a full pulse. CPU clock on latency is 2 or 3 CPU clocks while the CPU clock off latency is 2 or 3 CPU clocks.
CPUCLK
(Internal)
PCICLK_F
(Free-running)
CPU_STOP# PCI_STOP# PWR_DWN# CPUCLK
(External)
CPU_STOP# Timing Diagram Notes: 1. All timing is referenced to the CPUCLK. 2. The Internal label means inside the chip and is a reference only. This in fact may not be the way that the control is designed. 3 CPU_STOP# is an input signal that must be made synchronous to the free running PCI_F. 4. ON/OFF latency shown in the diagram is 2 CPU clocks. 5. All other clocks continue to run undisturbed. 6. PWR_DWN# PCI_STOP# are shown in a high state. 7. Diagrams shown with respect to 66 MHz. Similar operation as CPU = 100 MHz. PCI_STOP# is an input signal used to turn off the PCI clocks for low power operation. PCI clocks are stopped in the low state and started with a guaranteed full high pulse width. There is ONLY one rising edge of external PCICLK after the clock control logic.
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK_F
(Free-running)
CPU_STOP# PCI_STOP# PWR_DWN# PCICLK
(External)
PCI_STOP# Timing Diagram Notes: 1. All timing is referenced to the CPUCLK. 2. PCI_STOP# signal is an input signal which must be made synchronous to PCI_F output. 3 Internal means inside the chip. 4. All other clocks continiue to run undisturbed. 5. PWR_DWN# CPU_STOP# are shown in a high state. 6. Diagrams shown with respect to 66 MHz. Similar operation as CPU = 100 MHz.
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PI6C105 Precision Clock Synthesizer for Mobile PCs
The PWR_DWN#, which is used to place the device in a very low power state, is an asynchronous active low input. Internal clocks are stopped after the device is put in power down mode.
CPUCLK
(Internal)
The power on latency is less than 3ms. PCI_STOP# and CPU_STOP# are "don't cares" during the power down operations. The REF clock is stopped in the LOW state as soon as possible.
PCICLK
(Internal)
PWR_DWN# CPUCLK
(External)
PCICLK
(External)
VCO
Crystal
Notes: 1. All timing is referenced to the CPUCLK. 2. The Internal label means inside the chip and is a reference only. 3. PWR_DWN# is an asynchronous input and metastable conditions could exist. The signal is synchronized inside the part. 4. The Shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown wth respect to 66 MHz. Similar operations as CPU = 100 MHz.
PWR_DWN# Timing Diagram
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ............................................................ 65C to +150C Ambient Temperature with Power Applied ............................. 0C to +70C 3.3V Supply Voltage to Ground Potential ............................. 0.5V to +4.6V 2.5V Supply Voltage to Ground Potential ............................. 0.5V to +3.6V DC Input Voltage ................................................................... 0.5V to +4.6V
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC Electrical Characteristics (TA = 0C to +70C)
PI6C105 Condition Powerdown Mode (PWRDWN# = 0) Active 66 MHz SEL 100/66# = 0 Active 100 MHz SEL 100/66# = 1 M ax. 2.5V Supply Cons umption M ax. dis cre te cap loads , VDDCPU = 2.625V All s tatic inputs = VDD or VSS 100A 72mA 100mA M ax. 3.3V Supply Cons umption M ax. dis cre te cap loads , VDD = 3.465V All s tatic inputs = VDD or VSS 500A 170mA 170mA
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PI6C105 Precision Clock Synthesizer for Mobile PCs
DC Operating Specifications
Symbol VDD = 3.3V 5% VIH3 VIL3 IIL VDD2 = 2.5V 5% VOH2 VOL2 VDD = 3.3V 5% VOH3 VOL3 VDD = 3.3V 5% VPOH VPOL PCI Bus output high voltage PCI Bus output low voltage IOH = - 1mA IOL = 1mA 2.4 0.55 V Output high voltage Output low voltage IOH = - 1mA IOL = 1mA 2.0 0.4 V Output high voltage Output low voltage IOH = - 1mA IOL = 1mA 2.0 0.4 V Input high voltage Input low voltage Input leakage current 0 < VIN < VDD VDD 2.0 VSS - 0.3 -5 VDD +0.3 0.8 +5 V Parame te rs Conditions M in. M ax. Units
CIN CXTAL COUT LPIN TA
Input pin capacitance Xtal pins capacitance Output pin capacitance Pin Inductance Ambient Temperature No airflow 0 13.5 18.0
5 22.5 6 7 70 nH C pF
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PI6C105 Precision Clock Synthesizer for Mobile PCs
Buffer Specifications
Buffe r Name CPU REF, 48/24 MHz PCI VDD Range (V) 2.375 - 2.625 3.135 - 3.465 3.135 - 3.465 Impe dance (W) 13.5 - 45 20 - 60 12 - 55 Buffe r Type Type 1 Type 3 Type 5
Type 1: CPU Clock Buffers (2.5V)
Symbol IOHMIN IOHMAX IOLMIN IOLMAX tRH tFH Parame te rs Pull- up current Pull- up current Pull- down current Pull- down current 2.5V Type 1 output rise edge rate 2.5V Type 1 output fall edge rate Conditions VOUT = 1.0V VOUT = 2.375V VOUT = 1.2V VOUT = 0.3V 2.5V 5% @ 0.4V- 2.0V 2.5V 5% @ 2.0V- 0.4V 1 1 27 30 4 4 V/ns M in. - 27 - 27 mA Typ. M ax. Units
Type 3: REF Buffers (3.3V)
Symbol IOHMIN IOHMAX IOLMIN IOLMAX tRH tFH Parame te rs Pull- up current Pull- up current Pull- down current Pull- down current 3.3V Type 3 output rise edge rate 3.3V Type 3 output fall edge rate Conditions VOUT = 1.0V VOUT = 2.375V VOUT = 1.2V VOUT = 0.3V 3.3V 5% @ 0.4V- 2.4V 3.3V 5% @ 2.4V- 0.4V 0.5 0.5 29 27 2 2 V/ns M in. - 29 - 23 mA Typ. M ax. Units
Type 5: PCI Clock Buffers (3.3V)
Symbol IOHMIN IOHMAX IOLMIN IOLMAX tRH tFH Parame te rs Pull- up current Pull- up current Pull- down current Pull- down current 3.3V Type 5 output rise edge rate 3.3V Type 5 output fall edge rate Conditions VOUT = 1.0V VOUT = 3.135V VOUT = 1.95V VOUT = 0.4V 3.3V 5% @ 0.4V- 2.4V 3.3V 5% @ 2.4V- 0.4V 1 1 30 38 4 4 V/ns M in. - 33 - 33 mA Typ. M ax. Units
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PI6C105 Precision Clock Synthesizer for Mobile PCs
AC Timing
Figure 1. Hos t Clock to PCI CLK Offs e t tHKP (2.5V) tHKH (2.5V) tHKL (2.5V) tHRISE (2.5V) tHFALL (2.5V) tJITTER (2.5V) Duty Cycle (2.5V) tHSKW (2.5V) tPZL, tPZH tPLZ, tPHZ tHSTB tPKP tPKPS
tPKH
Parame te rs Host CLK period Host CLK high time Host CLK low time Host CLK rise time Host CLK fall time Host CLK Jitter Measured at 1.25V Host Bus CLK Skew Output enable delay Output disable delay Host CLK Stabilization from power- up PCI CLK period PCI CLK period stability PCI CLK high time PCI CLK low time PCI Bus CLK Skew Host to PCI Clock Offset PCI CLK Stabilization from power- up
66 M Hz M in. 15.0 5.2 5.0 0.4 0.4 1.6 1.6 250 45 55 175 1.0 1.0 8.0 8.0 3 30.0 500 12.0 12.0 500 1.5 4.0 3 M ax. 15.5
100 M Hz M in. 10.0 3.0 2.8 0.4 0.4 1.6 1.6 250 45 55 175 1.0 1.0 8.0 8.0 3 30.0 500 12.0 12.0 500 1.5 4.0 3 M ax. 10.5
Units
ns
ps % ps ns ms ns ps ns ps ns ms
tPKL tPSKW tHPOFFSET tPSTB
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3.3V Clocking Interface (TTL)
2.5V 2.0 Clocking 1.25 Interface 0.4
Host CLK
Host CLK
PCI CLK
PCI CLK
tHPOFFSET
2.4 1.5 0.4
Figure 1. Host Clock and PCI CLK Timing
Figure 2. Clock Output Waveforms
1.25V
tHrise tPrise
1.25V
Output Buffer
tHSKW
1.5V
tHKH
tPKH
1.5V
259
tPSKW
Duty Cycle Test Load
tHKP
tPKP
tHfall
tPfall
Test Point
PI6C105 Precision Clock Synthesizer for Mobile PCs
1.25V
tHKL
tPKL
1.25V
1.5V
tHPOFFSET
2.5V
3.3V
VSS
VSS
VSS
2.5V
3.3V
VSS
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PI6C105 Precision Clock Synthesizer for Mobile PCs
Minimum and Maximum Expected Capacitive Loads
Clock CPU Clocks (HCLK ) PCI Clocks (PCLK ) REF, 48MHz M in. Load 10 30 10 M ax. Load 20 30 20 pF Units Note s 1 device load, possible 2 loads Meets PCI 2.1 requirements 1 device load
Notes: 1. Maximum rise/fall times are guaranteed at maximum specified load for each type of output buffer. 2. Minimum rise/fall times are guaranteed at minimum specified load for each type of output buffer. 3. Rise/fall times are specified with pure capacitive load as shown. Testing is done with an additional 500 resistor in parallel.
1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value for CI is 10pF. RS Series resistor value can be increased to reduce EMI provided that the rise and fall time are still within the specified values. 2. Minimize the number of vias of the clock traces. 3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing clock traces from plane to plane (refer to rule #2). 4. Position clock signals away from signals that go to any cables or any external connectors.
Design Guidelines to Reduce EMI
21$+#
2 CPUCLK CL 6 PCICLK CL Rs REF CL 1 Device load Rs Meets PCI2.1 Req. Rs 1 Device load
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PS8316
03/15/99
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Note: This is only a suggested layout. There may be alternate solutions depending on actual PCB design and layout. As a general rule, C2-C6 should be placed as close as possible to their respective VDD.
PCB Layout Suggestion
261
Recommended capacitor values: C2-C6 .............. 0.1uF, ceramic C1, C7 ............ 22uF
PI6C105 Precision Clock Synthesizer for Mobile PCs
PS8316
03/15/99
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Ordering Information
28-Pin SSOP Package Data
P I6C105H
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
P/N
28-pin SSOP P a cka ge
D e s cription
262
PI6C105 Precision Clock Synthesizer for Mobile PCs
PS8316
03/15/99

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